1. Field of the Invention
The present invention relates to a testing apparatus and a method of testing a semiconductor device, and a more particularly to a technique for dispensing with or easing timing correction and temperature control and a technique for setting a skew rate of a signal (i.e., inclination of its waveform) at a desired or predetermined value for testing a semiconductor device.
2. Description of the Background Art
There is a growing demand that recent semiconductor integrated circuits should have increasingly faster response to and from external circuits. Particularly, semiconductor integrated circuits operating in synchronization with external clocks are becoming enhanced to have higher frequencies. With higher frequencies, a test rate is reduced, which results in a reduction in a setup time and a hold time of data that should be determined within the rate. For instance, each AC parameter (setup time, hold time and access time) between an external clock and a control signal is becoming smaller and smaller (see FIGS. 12 and 13 and FIGS. 14 and 15).
Therefore, an apparatus for testing a semiconductor integrated circuit needs to have capability of receiving and judging a high-frequency signal and to have a function of adjusting a timing shift or a phase shift (hereinafter also referred to as xe2x80x9cskewxe2x80x9d) of each signal with high accuracy (hereinafter also referred to as xe2x80x9ccalibrationxe2x80x9d). For instance, in order to carry out an accurate testing of a device under test that uses specifications in which the testing apparatus is required to have a skew accuracy of at leastxc2x1several tens of ps when a setup time is set at several hundreds of ps or less. Conventional calibration is discussed, for example, in Japanese Patent Application Laid-Open Nos. 58-201121 and 4-127073.
Now in reference to FIGS. 16 and 17, explanation will be given on a conventional timing correction method.
In general, a testing apparatus is provided with a pin electronics including a plurality of sets of a driver 131P and a comparator 132P (hereinafter also referred to as xe2x80x9ctester pinsxe2x80x9d). The driver 131P receives a signal from a timing generator 110 to generate and output a test signal to a device under test (a semiconductor integrated circuit). The output signal of the driver 131P is lead to a wiring 330P on a testing board 300P through a relatively large general-purpose board and a coaxial cable, and is inputted to a terminal 12 of a semiconductor device 10 under test from the wiring 330P through a wiring of a socket 309. The semiconductor device 10 outputs a signal in response to the input signal, and the output signal from the device under test is received by the comparator 132P along the reverse path to the output signal of the driver 131P. The comparator 132P carries out a level judgment of the received signal at a predetermined timing. The testing apparatus is programmable to output and judge signals at various levels and timings such that semiconductor integrated circuits having various functions can be tested.
Timing correction on the plurality of tester pins is carried out using variable delay circuits 160P connected to input terminals of drivers 131P prior to the start of a test in such a manner that signals are inputted to respective terminals 12 of the semiconductor device 10 at the same timing.
Among conventional timing correction methods is a method of performing calibration with high accuracy at a socket end serving as a connecting part of electrically connecting a device under test and a testing apparatus. In this correction method, the timing is adjusted at each tester pin by using an oscilloscope or the reference comparator 133P.
Another conventional timing correction method is a method of adjusting a differential delay of a driver signal generated by a testing apparatus while measuring the delay with a comparator end of the testing apparatus in the state, for example, in which a jig dedicated for short-circuiting between pins of a socket is mounted on the socket.
Information acquired by timing adjustment is stored in the testing apparatus and is reflected as correction data per tester pin when conducting testing.
It is desirable that environments including the ambient temperature at timing adjustment are equivalent to those at conducting testing. This is because a discrepancy in environments between timing adjustment and testing results in a discrepancy in properties of respective components forming the timing generator 110 and the delay circuit 160P, which is a factor that causes an error.
Therefore, in recent testing apparatuses, a solution whose temperature is maintained almost constant, for example, is circulated, thereby preventing an increase in a temperature of a main circuit that is to be a key part of timing generation and the like in the testing apparatus due to the ambient temperature and self-heat-generation of the main circuit. With such temperature control, environments at calibration are maintained during testing, thereby achieving testing with high accuracy having a minimized error.
In light of the trend toward higher frequencies of signals, testing in consideration for the highest frequency is required. More specifically, an output signal of a driver is required to have fast rise and fall times. When a circuit having the standard of start and finish timings such as a setup time and a hold time at the level of 90% of a signal amplitude is tested with a signal having rise and fall times faster than those under an actual operation, operating conditions may be eased compared to those under the actual operation.
As described above, a conventional testing apparatus is required to have capability of receiving and judging a high-frequency signal and to have a function of adjusting a skew of each signal with high accuracy (calibration), which arises a problem in that adjustment of the testing apparatus becomes complicated. More specifically, adjusting a timing error to fall within the aforementioned range ofxc2x1several tens of ps requires a complicated adjusting mechanism and a mechanism for maintaining it. Moreover, periodic verifications and recorrections become necessary in order to maintain adjusted properties constant with the passage of time.
There is another problem in that the conventional testing apparatus includes temperature control means for equalizing environments at timing adjustment and at testing, which thus becomes complicated and expensive.
With the aforementioned trend toward higher frequencies of signals, an output signal of a driver is required to have fast rise and fall times. This, however, arises still another problem in that the rise and fall times of the output signal of the driver are generally determined as properties of a driver chip in the conventional testing apparatus, and cannot be adjusted, for example, by a program of the testing apparatus to various values.
An object of the present invention is to provide a testing apparatus and a method of testing a semiconductor device, capable of dispensing with or easing timing correction and temperature control.
Another object of the present invention is to provide a method of obtaining a signal having a predetermined slew rate (inclination of waveform) and testing a semiconductor device with the signal.
The testing apparatus according to the present invention includes a test circuit including a pin electronics. The pin electronics includes a plurality of drivers, each of which can output signals having various waveforms. The testing apparatus further includes a testing board for electrically connecting the test circuit and a semiconductor device under test. The testing board includes a plurality of first wirings each having one end connected to a common point and the other end connected to one of the plurality of drivers, and a plurality of second wirings each having one end connected to the common point and the other end connected to a terminal of the semiconductor device.
With the testing apparatus, a signal is inputted to the other end of each of the first wirings such that a plurality of signals are composed at the common point (generation of composite wave), and the composite wave is inputted to each terminal of the semiconductor device under test through each of the second wirings. Since the composite wave is inputted to each of the terminals of the semiconductor device in this way, the signals inputted to the terminals can be brought into phase with each other. Thus, it is possible to dispense with timing correction for aligning the phase of the signals inputted to the respective terminals of the semiconductor device or to ease the accuracy of adjustment of such timing correction. This can achieve an improved productivity of a semiconductor device. Further, since timing correction becomes unnecessary or simplified, it is possible to dispense with or ease temperature control and equipment for equalizing the ambient temperature at timing correction with that at an actual testing. Therefore, a low-cost testing apparatus having a simple configuration can be provided.
The method of testing a semiconductor device according to the present invention is performed by inputting a plurality of signals to terminals of a semiconductor device under test, the plurality of signals are composed to generate a composite wave, and the composite wave is inputted to each of the terminals of the semiconductor device.
With the method, since the composite wave is inputted to each of the terminals of the semiconductor device, the signals inputted to the respective terminals can be brought into phase with each other. Thus, it is possible to dispense with timing correction for aligning the phase of the signals inputted to the respective terminals of the semiconductor device or to ease the accuracy of adjustment of such timing correction. Further, since timing correction becomes unnecessary or simplified, it is possible to dispense with or ease temperature control and equipment for equalizing the ambient temperature at timing correction with that at an actual testing.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.